The present invention relates to the field of semiconductor manufacture, and more specifically to a universal carrier tray for holding integrated circuit devices.
The Plastic Ball Grid Array (PBGA) package is a relatively new package design which is gaining popularity as an attractive package solution for memory and microprocessor devices. It offers a high-density package with a smaller form/fit factor than a comparable leadcount quad flat pack package. More importantly, it is designed with solder balls instead of leads, and they are more durable and loosely pitched than the fragile package leads of a comparable surface-mount component. This results in higher board yields.
The PBGA package consists of a thin Printed Circuit Board (PCB) made of a BT epoxy laminate, double-sided, and overlaid with copper over which metallized wire bond pads and a die pad are fabricated. The wirebond pads extend outward to plated through-hole-vias located around the board""s periphery. These vias provide the electrical continuity from the top of the board to the other side where copper traces run from the holes to a matrix of solder bumps. The bumps are soldered onto a land pattern on a circuit board in the end-use application. A solder mask is photo defined on the backside of the package to contain the flow of solder during board assembly.
The die is attached to the die pad using a standard epoxy die attach method. Gold ball bonding is used to connect the die pads to the wire bond pads, and the die of overmolded with silicone-modified, epoxy novolac encapsulation material to protect it.
The PBGA package design offers many advantages over other high leadcount packages. Because of the small package size, the BGA offers significant savings in board real estate, occupying about 51% of the space a comparable quad flat pack (QFP) requires. It has a lower profile, too, about one third as thick as a plastic quad flat pack (PQFP) package.
The BGA offers superior electrical performance because the shorter wirebond lengths in it help reduce inductance. Comparing a 169-ball BGA to a 160-ball PQFP, the BGA shows a 31 percent reduction in signal capacitance and a 46 percent reduction in signal time delay.
Studies have been conducted that show the BGA to thermally outshine a comparable PQFP when it is fabricated with xe2x80x9cthermal viasxe2x80x9d (i.e., through-hole vias) underneath the die pad. These vias allow heat generated by the device to flow to the board, which would improve thermal performance provided the board has a conducting plane built into it. However, thermal data shows that a thermal performance of the BGA (without thermal vias) is not as good as a comparable PQFP. When comparing a BGA with thermal vias to a PQFP with a heat sink attached to the lead frame, the BGA still does not perform as well. To more accurately ascertain the performance of a BGA, the specific end-use application environment needs to be considered.
The pitch of the solder balls on a BGA is far more manageable during board assembly, at 1.0 to 1.5 mm, than the typical of 0.5-mm pitch of high lead count Quad Flat Packs (QFPs).
BGAs can be handled with the same pick-and-place equipment that is used for conventional surface-mount devices, including solder reflow methods. During reflow assembly, the wetting action of the solder balls tends to pull them into alignment so that placement of the component on the solder land does not need to be nearly as precise as with a QFP. The alignment can be off by as much as 6 milsxe2x80x94more forgiving than the 3 mils (0.076 mm) required for fine lead-pitch QFPs.
New BGA packages are constantly being developed having varying body sizes, number of solder balls, and package design including cavity-up or cavity-down configurations, as well as interconnections formed using wirebonding or flip-chip technology. Typically, as each new BGA package is designed, a corresponding tray with holes configured to receive the solder balls on the BGA must be produced. This process is both time-consuming and costly.
There exists a need for an effective product carrier tray for a semiconductor device which eliminates problems associated with the requirement for a new product carrier tray for each new product.
There is also a need for an effective product carrier that eliminates the expense and long lag time associated with designing a new product carrier tray for each new semiconductor device.
According to one aspect of the invention, a carrier tray is provided for holding a semiconductor device. The carrier tray includes a two dimensional array of regularly spaced rows and columns of holes having one and only one pitch and having one and only one pocket size. The holes are configured to receive a solder ball of a ball grid array package.
Another aspect of the present invention is a method for manufacturing such a semiconductor carrier. The method includes the step of molding plastic into the desired configuration.
A further aspect of the present invention is an assembly that includes a carrier tray for holding a semiconductor device. The carrier tray includes: a two dimensional array of regularly spaced rows and columns of holes having one and only one pitch and one and only one pocket size, and the holes are configured to receive a solder ball of a ball grid array package. The assembly further includes at least two differently sized ball grid array packages comprising solder balls engaged in the holes of the carrier tray.
Other advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description. The embodiments shown and described provide illustration of the best mode contemplated for carrying out the invention. The invention is capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings are to be regarded as illustrative in nature, and not as restrictive.